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Ieee Transactions On Very Large Scale Integration (vlsi) SystemsSCIE

國際簡稱：IEEE T VLSI SYST 參考譯名：超大規模集成 (vlsi) 系統上的 Ieee 事務

中科院分區
2區
CiteScore分區
Q1
JCR分區
Q2

基本信息：: ISSN：1063-8210; E-ISSN：1557-9999; 是否OA：未開放; 是否預警：否; TOP期刊：是

出版信息：: 出版地區：UNITED STATES; 出版商：Institute of Electrical and Electronics Engineers Inc.; 出版語言：English; 出版周期：Bimonthly; 出版年份：1993; 研究方向：工程技術-工程：電子與電氣

評價信息：: 影響因子：2.8; H-index：95; CiteScore指數：6.4; SJR指數：0.937; SNIP指數：1.516

發文數據：: Gold OA文章占比：7.13%; 研究類文章占比：99.59%; 年發文量：241; 自引率：0.0714...; 開源占比：0.0933; 出版撤稿占比：0; 出版國人文章占比：0.15; OA被引用占比：0

投稿咨詢加急見刊

英文簡介期刊介紹 CiteScore數據中科院SCI分區 JCR分區發文數據常見問題

英文簡介Ieee Transactions On Very Large Scale Integration (vlsi) Systems期刊介紹

The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

期刊簡介Ieee Transactions On Very Large Scale Integration (vlsi) Systems期刊介紹

《Ieee Transactions On Very Large Scale Integration (vlsi) Systems》自1993出版以來，是一本工程技術優秀雜志。致力于發表原創科學研究結果，并為工程技術各個領域的原創研究提供一個展示平臺，以促進工程技術領域的的進步。該刊鼓勵先進的、清晰的闡述，從廣泛的視角提供當前感興趣的研究主題的新見解，或審查多年來某個重要領域的所有重要發展。該期刊特色在于及時報道工程技術領域的最新進展和新發現新突破等。該刊近一年未被列入預警期刊名單，目前已被權威數據庫SCIE收錄，得到了廣泛的認可。

該期刊投稿重要關注點：

預計審稿時間：一般,3-6周
國際TOP期刊
工程技術
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
SCIE
中科院2區
非預警

Cite Score數據（2024年最新版）Ieee Transactions On Very Large Scale Integration (vlsi) Systems Cite Score數據

CiteScore：6.4
SJR：0.937
SNIP：1.516

學科類別	分區	排名	百分位
大類：Engineering 小類：Electrical and Electronic Engineering	Q1	195 / 797	75%
大類：Engineering 小類：Hardware and Architecture	Q2	51 / 177	71%
大類：Engineering 小類：Software	Q2	124 / 407	69%

CiteScore 是由Elsevier(愛思唯爾)推出的另一種評價期刊影響力的文獻計量指標。反映出一家期刊近期發表論文的年篇均引用次數。CiteScore以Scopus數據庫中收集的引文為基礎，針對的是前四年發表的論文的引文。CiteScore的意義在于，它可以為學術界提供一種新的、更全面、更客觀地評價期刊影響力的方法，而不僅僅是通過影響因子(IF)這一單一指標來評價。

歷年Cite Score趨勢圖

中科院SCI分區Ieee Transactions On Very Large Scale Integration (vlsi) Systems 中科院分區

中科院 2023年12月升級版 綜述期刊：否 Top期刊：否

大類學科	分區	小類學科	分區
工程技術	2區	COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣	2區 3區

中科院分區表 是以客觀數據為基礎，運用科學計量學方法對國際、國內學術期刊依據影響力進行等級劃分的期刊評價標準。它為我國科研、教育機構的管理人員、科研工作者提供了一份評價國際學術期刊影響力的參考數據，得到了全國各地高校、科研機構的廣泛認可。

中科院分區表 將所有期刊按照一定指標劃分為1區、2區、3區、4區四個層次，類似于“優、良、及格”等。最開始，這個分區只是為了方便圖書管理及圖書情報領域的研究和期刊評估。之后中科院分區逐步發展成為了一種評價學術期刊質量的重要工具。

歷年中科院分區趨勢圖

JCR分區Ieee Transactions On Very Large Scale Integration (vlsi) Systems JCR分區

2023-2024 年最新版

按JIF指標學科分區	收錄子集	分區	排名	百分位
學科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE	SCIE	Q2	23 / 59	61.9%
學科：ENGINEERING, ELECTRICAL & ELECTRONIC	SCIE	Q2	151 / 352	57.2%

按JCI指標學科分區	收錄子集	分區	排名	百分位
學科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE	SCIE	Q2	26 / 59	56.78%
學科：ENGINEERING, ELECTRICAL & ELECTRONIC	SCIE	Q2	149 / 354	58.05%

JCR分區的優勢在于它可以幫助讀者對學術文獻質量進行評估。不同學科的文章引用量可能存在較大的差異，此時單獨依靠影響因子(IF)評價期刊的質量可能是存在一定問題的。因此，JCR將期刊按照學科門類和影響因子分為不同的分區，這樣讀者可以根據自己的研究領域和需求選擇合適的期刊。

歷年影響因子趨勢圖

發文數據

2023-2024 年國家/地區發文量統計

國家/地區數量
USA300
CHINA MAINLAND163
India72
Taiwan70
South Korea67
Canada46
GERMANY (FED REP GER)42
Singapore38
Iran36
Japan24

本刊中國學者近年發表論文

1、A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
Author: Bai, Fujun; Wang, Song; Jia, Xuerong; Guo, Yixin; Yu, Bing; Wang, Hang; Lai, Cong; Ren, Qiwei; Sun, Hongbin

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 128-141. DOI: 10.1109/TVLSI.2022.3219437
2、A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-mu W Embedded RRAM and Reconfigurable Strong PUF
Author: Ren, Qirui; Huo, Qiang; Chen, Zhisheng; Gao, Qi; Wang, Yiming; Yang, Yiming; Wu, Hao; Fu, Xiangqu; Xu, Xiaoxin; Luo, Qing; Gao, Jianfeng; Chen, Chengying; Zhao, Xiaojin; Lei, Dengyun; Wang, Xinghua; Zhang, Feng; Chen, Yong; Mak, Pui-In

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 243-252. DOI: 10.1109/TVLSI.2022.3222522
3、A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique
Author: Wang, Yujia; Zhang, Jincheng; Chen, Yong; Ren, Junyan; Ma, Shunli

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 233-242. DOI: 10.1109/TVLSI.2022.3225967
4、Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method
Author: Wang, Jun; Luo, Yuhuan; Guo, Wenting; Wu, Feng; Chu, Xiuqin

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 210-218. DOI: 10.1109/TVLSI.2022.3225533
5、Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors
Author: Tan, Hongbing; Tong, Gan; Huang, Libo; Xiao, Liquan; Xiao, Nong

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 253-266. DOI: 10.1109/TVLSI.2022.3226185
6、A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs
Author: Qiu, Lei; Meng, Tianyi; Yao, Bingbing; Du, Zihao; Yuan, Xiaohua

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 152-156. DOI: 10.1109/TVLSI.2022.3224237
7、BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks
Author: Li, Hongyan; Lu, Hang; Wang, Haoxuan; Deng, Shengji; Li, Xiaowei

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 90-103. DOI: 10.1109/TVLSI.2022.3221732
8、Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders
Author: Gao, Zhen; Shi, Jinchang; Liu, Qiang; Ullah, Anees; Reviriego, Pedro

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 142-146. DOI: 10.1109/TVLSI.2022.3224137